Montgomery Multiplication with a Serial to Parallel Multiplier

ABSTRACT

Elliptic Curve Cryptography (ECC) has become a strong and effective method for secure data protection and communication. Montgomery multiplication is a foundation and key operation for point multiplication in ECC. In Elliptic Curve Cryptography (ECC), Montgomery multiplication is a commonly used method for expediting modular arithmetic operations. However, typical Montgomery multipliers have high latency and large area requirements, which limits their application in contexts with limited resources. In this study, a novel design for a high-speed, small-area Montgomery multiplication method using a Serial to Parallel Multiplier (SPM) is proposed and put into practise for usage in ECC applications. The main goal of this research is to maximise computational Montgomery multiplication efficiency while minimising hardware resource footprint. To accomplish this, the study uses a novel strategy that takes advantage of the parallelism that SPM naturally provides while optimising them specifically for ECC operations. This device is specifically designed to meet the specific needs of ECC, assuring compatibility with various security levels and curve parameter ranges. Modern Very Large-Scale Integration (VLSI) techniques are used in the implementation to strike a balance between fast processing and small silicon area requirements. Additionally, this research investigates the possibility of hardware acceleration of ECC processes, which is increasingly important in contexts with limited resources, such as embedded systems and IoT devices. In comparison to previous techniques, the proposed SPM-based Montgomery multiplier considerably reduces latency by performing one modular multiplication in a single clock cycle. The suggested SPM-based Montgomery multiplier can also minimise the area by using the same hardware resources for addition and multiplication operations. As a result, this study makes a contribution to the field by developing a low-area, high-performance Montgomery multiplication algorithm that meets the computational needs of ECC for secure communication and data security.

Keywords: Elliptic Curve Cryptography (ECC), Montgomery multiplication, Very Large-Scale Integration (VLSI), Serial to Parallel Multiplier (SPM), Delay, Data Security.

INTRODUCTION

Elliptic curve cryptography (ECC) is a public key encryption method founded on elliptic curve theory. It can be used to produce cryptographic keys more efficiently, quickly, and in smaller sizes. ECC is a substitute for the Rivest-Shamir-Adleman (RSA) cryptographic algorithm and is most frequently used for one-way email, data, and software encryption as well as digital signatures in cryptocurrencies like Bitcoin and Ethereum [1]. An elliptic curve is not an oval shape, but rather a looping line that intersects two axes, or lines on a graph that show where a point is located [2]. Along the graph’s x-axis, the curve is perfectly symmetrical, or mirrored. Systems that use public key cryptography, like ECC, combine two different keys through a mathematical procedure, which is then used to encrypt and decrypt data [3]. One is a private key that is only known by the sender and recipient of the data, while the other is a public key that is known to everyone. Instead of using the conventional approach of creating keys by multiplying big prime numbers, ECC creates keys using the characteristics of an elliptic curve equation [4] [5]. The process of repeatedly adding a point along an elliptic curve to itself is known as elliptic curve scalar multiplication. A key component of ECC, which is commonly used for digital signatures and secure communications is elliptic curve multiplication [6]. ECC is favoured among all public key algorithms because it offers higher security per key bit. However, ECC calculation requires a lot of mathematics and adds a lot of time for applications that require speed. The Montgomery multiplication is used in ECC to improve the speed of operation for cryptography [7].

Montgomery multiplication is a technique for quick modular multiplication that is frequently employed in number theory and cryptography. The American mathematician Peter L. Montgomery introduced this method in the year 1985 [8]. This strategy is used in ECC to speed up the computation of scalar multiplication, which is the process of repeatedly adding a point along an elliptic curve to itself. This method reduces the number of partial products and enhances the speed of multiplication process. The effectiveness of Montgomery multiplication in cryptography is closely related to safety of cryptographic methods [9] [10]. Fast modular multiplication is a crucial part of strong cryptographic solutions because it lessens the vulnerability to side-channel attacks that take advantage of time or power consumption patterns. This multiplication is used to create a cryptographic key. The time needed to generate strong cryptographic keys directly depends on the speed and effectiveness of Montgomery multiplication [11]. There are various multiplier circuits such as binary, array, booth, serial to parallel, Wallace tree and so many multipliers used in digital circuit. Among aforementioned multiplier circuits the serial to parallel multiplier is one of the efficient multipliers to improve the speed and reduce delay of multiplication process in circuits [12].

A serial-to-parallel multiplier is a kind of multiplier that multiplies two binary values by adding their partial products simultaneously [13]. It adds the partial products serially and is faster than a serial-serial multiplier. This multiplier multiplies two inputs in a serial manner and produces the final output in parallel format which means it receives the inputs one by one and processes them, then stores and generates all outputs simultaneously and hence the delay of the operation is reduced, increasing the operating speed. Also, it reduces the area and power consumption of the circuit. Power, delay and speed are important factors in determining system performance. This multiplier may be more suitable for many applications since it has less time delay. Montgomery multiplication used in ECC has some drawbacks. The computation takes longer and is more complicated since there are additional conversions to and from the Montgomery form [14]. As a result, it is ineffective for reductions of a single modular unit and only profitable for chains of modular operations. Due to the requirement to limit the final result to the [0, N] range, there may be security vulnerabilities introduced [15]. Attackers may be able to use timing variations or information about the operands or modulus that is revealed as a result. To overcome these limitations in existing method, a novelty of serial to parallel multiplier is introduced in Montgomery multiplication in this study. This introduced approach reduces the latency and increases the speed.

In this paper, the high speed and area efficient Montgomery multiplication with serial to parallel multiplier is proposed in ECC. This strategy increases the operating speed while reducing delay. The main objectives of this paper are as follows:

The group operation’s data path is optimized, the number of stages in the process is decreased, and the system’s performance is increased.

The recommended Montgomery method offers the benefit of lowering latency in comparison to many other algorithms.

In this work, a mathematical method for achieving the suggested multiplier structure is presented to reduce time delay.

The advantage of the suggested technique is that it allows for the right scheduling and projection functions to be chosen in order to derive the ideal architecture for ECC.

The layout of this essay is as follows. The related literature of Montgomery multiplication and their problem statement is listed in Section 2. The detailed architecture of suggested SPM with Montgomery is shown in Section 3. The analysis and outcomes of the experiment are covered in Section 5. The work of this article is summarised in Section 6.

LITERATURE REVIEW

In 2019, Li, et. al [16] have offered a unique architecture for point multiplication in elliptic curve encryption with an emphasis on speed optimisation. The suggested design consists of a modified Montgomery Ladder algorithm, a balanced full-precision multiplier, and a novel modular inversion architecture. In comparison to all other efforts, the suggested design has the lowest latency, which makes it extremely effective for point multiplication in elliptic curve encryption. However, most designs are less useful in real-world applications than lab trials since they can’t sustain high frequency in bigger fields. Future multiple-field point multiplication can be supported by the architecture by being updated to a reconfigurable design.

In 2020, Mehrabi, et. al [17] have suggested an RNS-based ECC core hardware for two types of elliptic curves, namely short Weierstraß and twisted Edwards curves, which are commonly utilised in security modules for secure communications in IoT applications. The effectiveness and speed of ECC point multiplication are further improved by the addition of high-speed SOR units and parallel computation in the RNS point arithmetic. In the study, an RNS-based ECC core hardware is proposed for secure communications in Internet of Things (IoT) applications, which can offer improved security for sensitive data. In addition to short Weierstraß and twisted Edwards curves, other families of elliptic curves, such as Montgomery curves or Hessian curves, may also benefit from the use of RNS-based ECC core technology.

In 2020, Rashid, et. al [18] have provided a high-speed hardware architecture for binary fields over GF (2¹⁶³) and GF (2⁵⁷¹) point multiplication (PM) computation of elliptic-curve encryption. The suggested design incorporates parallel modular multipliers, a serially connected adder, and two serially connected squarer units to decrease the computing time for PM calculation. For cryptographic applications, the study was suggested a high-speed elliptic-curve point multiplication (PM) architecture. provide point multiplication (PM) calculation for elliptic-curve encryption an effective, high-speed hardware design that reduces computation time and overall clock cycles. The potential of the suggested high-speed architecture for point multiplication (PM) computation in different cryptographic algorithms and field sizes may be investigated through further study.

In 2020, Abd-Elkader, et. al [19] have introduced the Montgomery Modular Multiplier (MMM) architecture’s FPGA-based optimised implementation. The suggested design’s innovative architecture increased both the maximum frequency and the area occupied on the intended FPGA. For use with generic GF(p), the suggested architecture is implemented as a modular multiplier for lightweight ECC. Throughput of this research has been improved and efficiency of implementation also had greatest performance.

In 2021, Zhao, et. al [20] focussed on enhancing the security and effectiveness of the Physical Unclonable Function (PUF) response encryption in Internet of Things (IoT) devices by utilising the Elliptic Curve Cryptography (ECC) technique with various key lengths. The point multiplication circuit based on a binary field with adjustable key lengths for ECC encryption is described in detail in this work. The Virtex-6 FPGA from Xilinx is used to implement the circuit. The circuit provides versatility in encryption operations by allowing the use of four key lengths (233, 283, 409, and 571) to suit the needs of PUF response encryption. There has been little exploration of potential trade-offs or difficulties posed by adjustable key lengths and how they may affect system performance as a whole. The point multiplication circuit should be further optimised to increase its effectiveness and use less resources.

In 2021, Ahmadpour and Jaberipur [21] have suggested a method for quick 16-bit residue channels for fast hardware Montgomery modular multiplication (MMM) implementation in residue number systems (RNS) for ultra-wide key-lengths up to 8192 bits. The suggested delta-independent modulo-(2-delta) adders, multipliers, and a unique mechanism for choosing moduli for base extension form the basis of the scheme. The differential power-analysis (DPA) attacks are prevented by the suggested approach for moduli selection for base extension, hence boosting the security of the cryptosystems. This approach required large storage area.

In 2022, Ibrahim, et. al [22] have suggested a one-dimensional bit-parallel semi-systolic multiplier for the Montgomery multiplication method, a key operation in cryptographic protocols, with low-area, low-energy, and high-speed. The suggested multiplier structure is different from earlier two-dimensional parallel systolic designs in that it has an area complexity of order O(m) rather than O(m2). The suggested multiplier design reduces space by a small amount while significantly reducing latency. This research recommended the upcoming project, the suggested multiplier design into the ECC crypto-processor were integrate to calculate the system’s total space, time, and energy savings.

In 2022, Charishmmaa, et. al [23] have suggested a redundant signed digit representation-based exportable application-specific instruction-set ECC processor. The processor had a high throughput modular divider and an effective modular adder in addition to significant pipelining. The study suggested a redundant signed digit representation-based, heavily pipelined, exportable application-specific instruction-set ECC processor. The processor’s significant pipelining can improve throughput and performance, enabling quicker execution of cryptographic procedures. creating a novel reversible gate and incorporating reversible logic into a comprehensive quantum processor capable of processing at extremely high speeds and using extremely little power was suggested for future study.

In 2022, Awaludin, et. al [24] have recommended the quickest implementation of ECC point multiplication over Curve448 as a high-performance architecture for ECC. By fully parallelizing and pipelining, it proposes a unique variation of the Karatsuba formula for asymmetric digit multiplier, lowering the number of DSPs needed while maintaining performance. The unique Karatsuba formula for asymmetric digit multiplier has some drawbacks that are not investigated, such as its application to other cryptographic methods or its performance with various operand widths. The suggested architecture’s viability and appropriateness for resource-constrained contexts would be shown by looking into the energy efficiency and power consumption of the system in future research.

In 2023, Jain and Bansod [25] have suggested an improved Montgomery algorithm for the efficient implementation of modular multiplication in cryptography in the framework of RSA method. Verilog is used to implement the method, while Vivado is used to simulate it. Utilising an FPGA NESYS 4 DDR hardware board, physical testing is conducted. In this work, an improved Montgomery method is proposed for the effective implementation of modular multiplication in cryptography. In this work, an improved Montgomery method is proposed for the effective implementation of modular multiplication in cryptography.

Problem Statement

Existing Montgomery multiplication techniques using various multipliers for ECC are discussed in this section. Table 2 depicts the comparison of contribution, methodology used in article, benefits, and drawbacks of various aforementioned research.

Table 2. Comparison of existing methods

PROPOSED METHODOLOGY

This section of the paper will discuss the recommended strategy. The truth is that rather simple modular arithmetic is the foundation upon which many complex encryption methods are constructed. The only operations that can be carried out on integers are addition, subtraction, multiplication, and division since integers are the only kind of numbers that can be utilised in modular arithmetic. All operations are only carried out in reference to a positive integer, also referred to as the modulus, in modular arithmetic. Montgomery multiplication is a technique for quickly conducting modular multiplication for public key cryptography techniques in ECC. This multiplication can be implemented in both software and hardware with less delay, power, and area. The need for conversions to and from the Montgomery space, which entail R’s multiplications and reductions, is one of the factors contributing to the longer Montgomery multiplication times. Time delay is the main factor to decide the system performance. To improve the efficiency of device, the time delay should be reduced. Therefore, the Serial to Parallel Multiplier is introduced instead of traditional multiplier in Montgomery multiplication. In SPM, the input is given to multiplier one by one serially and the multiplier unit processing it then generates the result in parallel mode. Hence the delay of the multiplication unit will be reduced and obviously power consumption also automatically reduced since it has less time delay. Figure 1 illustrates the basic structure of introduced method.

Figure 1. Block diagram of proposed Montgomery SPM

Montgomery Multiplication for ECC

An effective and quick modular multiplication may significantly speed up the total elliptic curve scalar multiplication process. Multiplication is a crucial operation in the ECC algorithm. Through a straightforward shift, Montgomery multiplication converts division by p into division by a power of 2, performing modular multiplication. In order to do all arithmetic operations in the Montgomery domain and subsequently convert back to the ordinary domain, the inputs must first be converted into the Montgomery domain. The modular multiplication of two numbers x and y modulo N (referred to as N-residues) using Montgomery’s approach is efficient and may be expressed as follows:

Mont (x,y)=xy R^-1 mod N (1)

The Montgomery multiplier for ECC uses registers, a systolic array, a comparator and a counter as displayed in Figure 2. This architecture’s inputs were taken as X, Y, and M 1- bit inputs at first, expanding to n bits later; START is the controller’s directive for taking the system out of standby DONE (signify end of operation) carries state and outputs.  Result outputs a single or n-bit result.

Figure 2. Architecture of Montgomery multiplier for ECC

The system stays in an IDLE state until the START command is applied to controller. The input signals X, Y, and M are pushed into register after giving START instruction. The register and counter are reset when START is interfaced, and the output value of the systolic array cells is then carried out in register. The controller increases the counter by 1 to enter the next state while it is in current one. When the counter reaches the value of 2(l+1), the comparator generates the Count-end signal, which causes the controller to enter the OUT state. The value for the RESULT output is simultaneously sent to the register. At the very end of the process, the acknowledgment signal DONE is set. The procedure is complete when the OUT state is met because RESULT is created from the register and signal DONE is set.

In the Montgomery technique, divisions in traditional reduction algorithms are swapped out for less expensive operations like shift and addition. The technique works well for calculations like modular exponentiation but is inefficient for a single modular multiplication. Algorithm 1 describes Montgomery modular multiplication, where n is the k-bit module, r=2^k, and (rxr^-1 – nxn’) =1 may be pre-computed. A 2k-bit addition, a k-bit conditional subtraction, and three k-bit multiplications are all included in the Montgomery multiplication. The algorithm of this multiplication is shown below:

Serial to Parallel Multiplier

A type of multiplier known as a serial-to-parallel multiplier is capable of quickly and effectively multiplying two binary values. It operates by multiplying the bits of the partial products in each column and shifting the results one at a time into a register. In digital signal processing and computer architecture, a serial to parallel multiplier is a digital circuit or algorithmic approach that effectively multiplies two integers by splitting the multiplication work into smaller, easier parts. A serial to parallel multiplier handles the multiplication bit by bit in a sequential manner as opposed to ordinary parallel multipliers, which execute simultaneous computations on all bits of the operands. The least significant bits of the operands are multiplied first, and the results are then accumulated. Before processing all of the operands’ bits, it shifts and multiplies the subsequent set of bits. The Least Significant Bit (LSB) of the product are available in serial while the Most Significant Bit (MSB) bits are available in parallel in the SPM. The MSB can be timed into a register at the end of (n + nl) clocks using the same clock source if nl is the number of clock intervals needed to cover the parallel adder delay. The SPM type multiplier is mainly used to reduce latency in digital circuit.

In SPM, the inputs are applied serial manner. The two inputs are represented in parallel which means each input bit is available simultaneously. A serial-to-parallel multiplier processes the bits sequentially as opposed to multiplying every bit simultaneously. The LSB of one of the numbers, let’s say B, is the beginning point, and it is multiplied by each bit of the other number, let’s say A, starting with the LSB of A. After each multiplication operation, the multiplier keeps moving bits of B to the left. The result bits are simultaneously moved to the left to align with B’s present location. The current bit of B is multiplied with all the bits of A at each step using an AND gate. As a result, the partial product is generated for that bit location. Finally, these partial products are added to produce a final result that is the product of two binary numbers. The final output bits are stored in accumulator unit. As B is processed, all of its components are added to the accumulation and B is shifted to the left as the process progresses. The sum of results in memory unit indicates the result of multiplying all the bits of B by all the bits of A. This multiplier has the benefit of reducing time delay since it produces the result in parallel. Power consumption will also be lower and speed of operation will improve due to low propagation delay. Figure 3 illustrates the model structure of SPM.

Figure 3. Architecture of Serial to Parallel Multiplier

The Montgomery multiplication is mainly used in cryptography technique to encrypt the data. Multiplication is a crucial part in ECC. The Montgomery multiplication is used in ECC to improve the speed of multiplication process. However, this technique has some limitations like it includes additional subtraction process. These extra steps in multiplication process may take longer time to complete the process. Due to this, the propagation delay will increase and speed performance will reduce. To overcome these drawbacks, SPM is introduced in Montgomery multiplication in this research. This technique will reduce time delay and increases the operating speed. So that power consumption of system obviously reduced. Figure 4 shows the diagram of Montgomery multiplication using SPM technique.

Figure 4. Architecture of Montgomery Multiplication with SPM for ECC

The goal of a design is to speed up the Montgomery multiplication used in ECC while using minimal resources by using proposed SPM in the multiplication process. In this work, the step of Montgomery multiplication method is replaced with serial to Parallel Multiplier strategy. This SPM is mainly suggested to reduce latency and delay. This system includes memory unit, control unit, adder, multiplexer, and multiplier parts. The input data is stored in memory unit through multiplexer and control unit controls all signals used for process such as read, enable, and shift lines. The SPM is proposed here instead of traditional multiplier used in Montgomery multiplication process. Additionally, this system has reset, clock and load signals. The load line is applied before an input data is given to register. The result of SPM is stored in accumulator and produce it in parallelly. So, this proposed method provides more efficiency in ECC.

RESULTS AND DISCUSSION

The proposed design was synthesized and simulated with Xilinx 14.7 ISE simulator tool using Verilog HDL. The proposed approach was used in Montgomery multiplication for ECC to improve the speed by reducing time delay. The main parameter for analysing speed and area of system is time delay and area. These parameters are evaluated in this chapter and obtained results were compared with existing models.

Simulation of Serial to Parallel Multiplier

Initially, the 8-bit serial to parallel multiplier is synthesized and simulated to verify its functionality. Figure 5 illustrates simulation waveform of 8-bit SPM.

Figure 5. Simulation result of Serial to Parallel Multiplier

Simulation result of Proposed SPM with Montgomery multiplication

In this study, the Serial to Parallel Multiplier approach is introduced in Montgomery multiplication instead of traditional multiplier. This Montgomery multiplication is mainly to used for cryptography to encrypt information. To reduce delay and increase speed of the device the SPM is used for multiplication in ECC. The proposed design was synthesized and simulated using Xilinx tool and obtained results were indicated in this study. The two inputs x and y are 192 bits applied for multiplication. Additionally, clock, reset, and start signals were applied to do the process. The registers are used to store the inputs and results of multiplier. The resultant images are shown in following figures 6 -8.

Comparison of Proposed method with RSA algorithm

The newly introduced SPM into Montgomery design was compared with existing strategy to analyse the performance of proposed design. The parameters such as LUT, FF, IOB, BUFG and delay were used to analyse the performance of the new design. This strategy is contrasted with the most recent one that was previously introduced. The proposed strategy was initially synthesized for 8-bit inputs and output waveform is displayed in Figure 6.

Figure 6. Simulation result of 8-bit proposed SPM Montgomery

In this work, the two 8-bit values are applied to the inputs x and y. The code was developed in Verilog HDL. The modulus input of this multiplication remains constant which is applied through code. The circuit multiplies these two 8-bit inputs and generates the remainder as result. The synthesis report was obtained and values are compared with most recent existing RSA Montgomery algorithm. Table 2 depicts the comparison results of proposed and existing method.

Table 2. Comparison of proposed with existing RSA Montgomery algorithm

The proposed SPM Montgomery approach is evaluated and resultant values are compared with existing RSA algorithm which is recently introduced. In this analysis, the proposed method has great improvement than existing RSA algorithm. Initially, the design was synthesized and simulated with 8- bits. The value of LUT, FF, Input Output Block (IOB), and Clock Buffer (BUFG) of proposed design was listed as 51, 33, 28, and 1 respectively while it was indicated as 64, 24, 35, and 1 for RSA Montgomery algorithm. This result indicates that, the new design has improved performance and thus this technique is well suited for ECC for encrypting data.

Simulation result of 192-bit proposed SPM Montgomery multiplication.

Figure 7 below depicts the RTL design of proposed SPM Montgomery Multiplication architecture. In hardware description languages (HDLs) like Verilog and VHDL, register-transfer-level extrapolation is used to build high-level models of a circuit from which lower-level views and, finally, actual routing, may be deduced. Figure 8 illustrates the top-level ports of proposed method.

Figure 7. RTL schematic of Proposed method

Figure 8. Top Level Ports of Proposed Technique

Figure 9 shows the simulation waveform of proposed SPM with Montgomery. This output waveform is generated using the code written in Verilog HDL. The two 192-bit inputs x and y are applied to the system and fixed modulus value is applied in code. The multiplication process was performed and remainder was generated as result(z). The reset, clock, and start signals were applied to perform the process.

Figure 9. Simulation Result of Montgomery with SPM

Analysis of Proposed design with various existing methods

The Proposed SPM Montgomery multiplication is evaluated and results were compared with several existing techniques which are currently in use. This section covered the performance analysis of proposed design and the obtained results were compared with some existing methods. The main objective of this study is to reduce time delay and reduce the design area. In this analysis, the parameters such as LUT, time delay and frequency were computed to verify the performance of newly designed method. Time delay is the most crucial parameter for improving system performance. The power consumption of design will reduce due to less time delay. LUT is another parameter to decide the area of design and it may vary according to complexity of circuit design. The proposed design was initially synthesized using 8-bits and it was discussed in previous section of this paper and the results were compared with existing RSA Montgomery algorithm. It was clearly said that, the suggested strategy in this study has great performance when compared to RSA algorithm. To improve the efficiency of proposed design, further the proposed design was synthesized using 192- bits and the time delay and frequency was noted. The obtained results were compared with some methods which are currently in practice such as Karatsuba, Reversible, modular Montgomery, and one-dimensional semi systolic. These aforementioned methods were used in Montgomery multiplication for ECC. Table 3 illustrates the evaluation of existing and proposed design.

Table 3. Comparison Proposed design with several existing method

The aforementioned table represents the comparison results. The proposed design has improved performance in all parameters. The LUT count of the design determines the area of circuit design. Some previous research study does not consider the LUT in their evaluation. However, this research evaluates LUT with few existing methods. From the analysis results, the newly developed Montgomery method has less LUT when compared to existing design such as Karatsuba and Modular Montgomery. The main parameter of this study is time delay and frequency determines the time delay. Therefore, the frequency and time delay are analysed and discussed in following section. Figure 10 displays the evaluation of time delay.

Figure 10. Analysis of Time delay

The aforementioned figure represents a time period comparison of existing and proposed design. The time delay is mentioned in nano seconds. The delay of Modular, 1-D semi systolic, Reversible, Karatsuba, and proposed Montgomery multiplication design are indicated as 19.3, 6.7, 22.6, 14, and 4.36 respectively. From the computation results, the newly developed design had a shorter delay than all other compared existing designs. This delay determines the power consumption and the analysis results clearly show that the proposed method will obviously reduce power since it produces least time delay. These delay values show that suggested strategy in this study has improved performance than other existing designs.

The processing time will be less when frequency increases. Therefore, the frequency is the second important parameter used to analyse the system performance. The frequency of developed design is evaluated and obtained values are compared with several design which are currently in use. The design with a higher frequency will have good performance. Figure 11 displays the frequency of proposed and existing designs.

Figure 11. Analysis of Frequency

The above graph was plotted from the values given in Table 3. The frequency value for proposed, Karatsuba, Reversible, 1-D Semi-systolic, and Modular Montgomery multiplication are indicated as 229.361, 125, 160, 10, and 135 respectively. The above frequency values are expressed in MHz. From the analysis results, the proposed design has the highest frequency when compared to all other existing techniques. The design with highest frequency achieves great performance in time delay, and speed of the circuit.

From the above evaluation, the proposed design achieves less delay, more LUT and frequency. The analysed parameters achieve the better value in all parameters when compared to various existing designs. Therefore, the suggested design in this study has great performance and speed of the system will be high since it has the shortest delay. This proposed SPM Montgomery multiplication design is well suited for ECC to encrypt information with less time and high speed.

CONCLUSION

In this article, the high speed and low area Montgomery multiplication using Serial to Parallel Multiplier for ECC was designed. The proposed design was synthesized and simulated using Xilinx ISE 14.7 simulator tool. The 8-bit SPM with Montgomery was synthesized and results were compared with RSA algorithm. In this comparison the SPM Montgomery has great performance when compared to RSA. Then the proposed design was implemented in 192-bits and obtained results were compared with various existing designs. The suggested processor’s implementation findings revealed the shortest data route at a maximum frequency of 229.361 MHz, which is the quickest recorded in the literature for completely LUT-based ECC processors. The processor can do a SPM Montgomery multiplication in 4.36 nanoseconds which is much less than several existing Montgomery multiplication methods. The main advantage of a proposed design is that it has a shorter delay and uses area efficiently which increases the operating speed in Montgomery multiplication used in ECC. Therefore, the proposed design is suitable for ECC to encrypt data with a shorter delay and a higher operating speed.

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